When it comes to technological advancements, there are very few hard-and-fast rules. But one that’s held up incredibly well is Moore’s Law, which posits that the number of transistors on a microchip will double every two years. While the fulfillment of this vision has changed our world in innumerable ways, the full benefit of the achievement is muted due to bottlenecks in the subsequent back-end packaging of these miracle devices.
Similarly, a 70-year-old technique called wire bonding, which mechanically tacks the two ends of a protruding wire, plays a dominant role in connecting nanometer-scale circuitry on a chip to mesoscale circuitry on a printed circuit board.
Given the fragility of these free-standing, 25-micron wires, they are enveloped in a protective overmolding that embeds further upscaling using a metal skeleton called a lead frame with exposed plated pins or pads that are soldered to the PCB. This multi-step process results in an oversized construct consuming about 10 times more space than the chip itself, and is repeated many times over as electronics products are composed of multiple chips.
Ultimately, the best way to improve semiconductor packaging may be to eliminate the traditional package altogether by directly mounting and connecting the bare chip or die onto the target substrate. This approach enables up to an 80% reduction in overall space claim—laterally and vertically—leading to significant savings in the size of a printed-wiring board with follow-on reductions in weight, material, and process costs. However, this significantly improved approach necessitates a paradigm shift in interconnect technology.
Optomec’s patented Aerosol Jet solution is an ultra-high resolution material deposition technology used to print functional electronic circuitry and related materials directly onto planar and non-planar surfaces at room temperature.
The process utilizes an innovative aerodynamic focusing technique to collimate a dense mist of material-laden microdroplets into a tightly controlled beam that can produce features as small as 5 microns—or as large as 5 centimeters or more—in a single pass.
Aerosol Jet is particularly well suited for printing onto undulating and fully 3D surfaces because it is a non-contact process that can tolerate a variable stand-off distance (1-5+ mm), and a variable angle of incidence (± 30 degrees). As such, it has the unique ability to print high-density, highly conductive traces from the top of a bare die down a step edge to a host circuit board, thereby creating a printed 3D Interconnect.
Optomec and its customers have industrialized this printed 3D Interconnect process for select use cases, including end products ranging from low to high I/O counts, thin to tall die, rigid to flex substrates, and across signal, RF, and power functions. Several early adopters have successfully transitioned to production—mostly for defense-oriented products with hundreds of thousands of units shipped.
Through these efforts, we have demonstrated that in addition to the significant size, weight, and cost reductions of a bare-die configuration, the conformal nature of the printed 3D Interconnect also has improved mechanical stability and substantially lower RF loss, especially for higher frequency 5G/mmWave+ applications.
Buoyed by the CHIPS Act, which includes a $4 billion investment in semiconductor packaging, Optomec is working to accelerate wider adoption with the development and dissemination of generic printable 3D Interconnect libraries that include design rules, process parameters, functional performance, and reliability data. There are also expanding efforts to apply Aerosol Jet to a broad range of other advanced 3D semiconductor packaging applications including die attach, die bumping, via filling, shielding, and tamper proofing.
Editor’s Note: Dave Ramahi unexpectedly died in late March. We extend our deepest sympathies to his family, co-workers, and friends.
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