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Product Title: Taking Advantage of Delay Correlation Effects to Design High Speed...

Updated from Personify: 2014-11-06

Personify Product Code: TP01PUB12

Personify Product ID:       126078

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Author: Dr Peter Menegay, Daniel L Notestein



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Published Date: 2001-01-10

Page Count: 8

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Product Type:   TECHPAPER




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Getting the best performance out of your silicon means squeezing every little bit of extra time out of your circuit. One way to improve system speed is to perform a delay correlation analysis during the early stages of your design and optimize your circuit to take advantage of the delay tracking between gates. The variation in delays between gates within a given IC is smaller than between gates on different ICs of the same type because of process and temperature variations across the ICs. Delay correlation between on-chip gates gives designers the ability to build circuits that can run faster than might seem possible when performing timing analysis using the worst case across-chip min/max delays provided by most chip manufacturers. Authors: Peter Menegay, Daniel L. Notestein, SynaptiCAD, Inc., Blacksburg, VA.


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